Assistant Professor  

Department of Computer Science, City University of Hong Kong, Tat Chee Ave, Kowloon, Hong Kong
Email: jasonxue at cityu.edu.hk Office: Y6428 Phone: 2788 9815



Research Interests

Teaching

  1. CS2115 Computer Organization

  2. CS3161 Operating System Principles

Publications

    2013        

    Conference
DATE     Profit maximization through process variation aware high level synthesis with speed binning, Zhao Mengying, Orailoglu Alex and Xue Chun Jason, Accepted in Design Automation and Test Europe, DATE 2013.
DATE     Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs, Dip Goswami, Alejandro Masrur, Reinhard Schneider, Chun Jason Xue and Samarjit Chakraborty, Accepted in Design Automation and Test Europe, DATE 2013.
DATE     Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems, Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng and Edwin Sha, Accepted in Design Automation and Test Europe, DATE 2013.

    2012        

    Conference
DAC     Quality-retaining OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices, Xiang Chen, Mengying Zhao, Jian Zheng, Yiran Chen, Chun Jason Xue, Accepted in Design Automation Conference, DAC 2012.
ICCAD   Active Compensation Technique for the Thin Film Transistor Variations and OLED Aging of Mobile Device Displays , Xiang Chen, Beiye Liu, Mengying Zhao, Chun Jason Xue, Xiaojun Guo and Yiran CHen, Accepted in ICCAD 2012.
ISPLED     MAC: Migration-Aware Compilation for STT-RAM based Hybrid Cache in Embedded Systems, Qingan Li, Jianhua Li, Liang Shi, Chun J. Xue and Yanxiang He, Accepted ISPLED 2012. (Best Paper Candidate)
LCTES     Compiler-Assisted Preferred Caching for Embedded Systems with STT-RAM based Hybrid Cache, Qingan Li, Mengying Zhao, Chun Jason Xue, Yanxiang He, Accepted LCTES 2012.
LCTES     WCET-aware Re-scheduling Register Allocation for Real-time Embedded Systems with Clustered VLIW Architecture, Yazhi Huang, Mengying Zhao, Chun Jason Xue, Accepted LCTES 2012. (Best Paper Candidate)
       
    Journal
TECS     Joint Variable Partitioning and Bank Selection Instruction Optimization for Partitioned Memory Architectures, TIANTIAN LIU, CHUN JASON XUE and MINMING LI, Accepted in ACM Transaction on Embedded Computing System (TECS) 2012.
TECS          Register Allocation for Embedded Systems to Simultaneously Reduce Energy and Temperature on Registers TIANTIAN LIU, ALEX ORAILOGLU, CHUN JASON XUE and MINMING LI, Accepted in ACM Transaction on Embedded Computing System (TECS)2012.
TECS     Write Activity Reduction on Non-Volatile Main Memories for Embedded Chip Multi-Processors, JINGTONG HU, CHUN JASON XUE, QINGFENG ZHUGE, WEI-CHE TSENG, EDWIN H.-M. SHA, Accepted in ACM Transaction on Embedded Computing System (TECS) 2012.
TECS     Management and Optimization for Non-volatile Memory based Hybrid Scratchpad Memory on Multi-core Embedded Processors, JINGTONG HU, QINGFENG ZHUGE, CHUN JASON XUE, WEI-CHE TSENG, EDWIN H.-M. SHA, Accepted in ACM Transaction on Embedded Computing System (TECS) 2012.
TVLSI   WCET-aware Re-scheduling Register Allocation for Real-time Embedded Systems with Clustered VLIW Architecture , Yazhi Huang, Liang Shi, Jianhua Li, Qingan Li, Chun Jason Xue, Accepted in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI) 2012.
TVLSI   Task Allocation on Non-Volatile Memory Based Hybrid Main Memory, Wanyong Tian, Yingchao Zhao, Liang Shi, Qingan Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen, Accepted in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI) 2012.
TVLSI     Cooperating Virtual Memory and Write Buffer Management for Flash-based Storage Systems, Liang Shi, Jianhua Li, Chun Jason Xue, and Xuehai Zhou, Accepted in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI) 2012.
TVLSI     Data Allocation Optimization for Hybrid Scratch Pad Memory with SRAM and Non-volatile Memory Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, and Edwin H.-M. Sha Accepted in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI) 2012.
TSP     Qingfeng Zhuge, Yibo Guo, Jingtong Hu, Wei-Che Tseng, Chun Jason Xue, Edwin Hsing-Mean Sha: Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling. IEEE Transactions on Signal Processing (TSP) 60(6): 3253-3263 (2012).
TODAES     Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou:"Hybrid Non-Volatile Disk Cache for High Performance and Energy Effficient Systems" , accepted in ACM Transactions on Design Automation of Electronic Systems (TODAES) 2012.
TC     J. Hu, Chun Jason Xue, W. Tseng, Q. Zhuge, S. Gu and E. H.-M. Sha:"Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories" , accepted in IEEE Transactions on Computers (TC) 2012.

    Journal Papers       

  1. J. Hu, W. Tseng, C. Xue, Q. Zhuge, Y. Zhao and E. H.-M. Sha, "Write Activity Minimization for Non-volatile Main Memory via Scheduling and Recomputation,"   in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), VOL.30 NO. 4, 584-592, April 2011.


  2. Q. Xu, C. Xue, E. H.-M. Sha, "Energy Efficient Joint Scheduling and Application Specific Interconnection Design,"   Accepted in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI) Aug, 2010.


  3. C. Xue, J. Hu, Z. Shao, and E. H.-M. Sha, "Iterational Retiming with Partitioning: Loop Scheduling with Complete Memory Latency Hiding"   in ACM Transaction on Embedded Computing System (TECS), Volume 9, Issue, 3, Feb. 2010, Pages 1-26.


  4. C.Q. Xu, C. Xue, J. Hu, and E. H.-M. Sha, "Optimizing Scheduling and Intercluster Connection for Application-Specific DSP Processorsﾡﾱ, in IEEE Transaction on Signal Processing (TSP), pp 4538-4548, Vol 57, Nov 11, Nov 2009.


  5. Q. Zhuge, C. Xue, M. Qiu, J. Hu and E. H.-M. Sha, "Timing Optimization via Nest-Loop Pipelining Considering Code Size"   in Journal of Microprocessors and Microsystems, Volume 32, Issue 7, October 2008, Pages 351-363.


  6. C. Xue, Z. Jia, Z. Shao, M. Wang, and E. H.-M. Sha, "Optimize Address Assignment with Array and Loop Transformation for minimizing schedule length"   in IEEE Transaction on Circuits and System (TCAS), 55(1), February 2008, pp 367-377.


  7. C. Xue, Z. Shao, Q. Zhuge, B. Xiao, M. Liu, and E. H.-M. Sha "Optimizing Address Assignment for Scheduling DSPs with Multiple Functional Units," in IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 9, pp. 976 - 980, September 2006.


  8. C. Xue, Z. Shao, and E. H.-M. Sha, "Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping"  in Journal of VLSI Signal Processing Systems (JVLSI), Vol. 47, No. 2, May 2007, pp. 153 - 167.


  9. Z. Shao , C. Xue , Q. Zhuge, M. Qiu, B. Xiao and E. H.-M. Sha, "Security Protection and Checking for Embedded System Integration Against Buffer Overflow Attacks via Hardware/Software" in  IEEE Transactions on Computers (TC), Vol. 55, No. 4, pp. 443-453, Apr. 2006.

  10. Z. Shao, C. Xue, Q. Zhuge, B. Xiao and E. H.-M. Sha, "Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP" in  ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 1, pp. 165-185, Jan. 2006.


  11. C. Xue, Z. Shao, M. Liu, M. Qiu, E. H.-M. Sha, " Optimizing Parallelism for Nested Loops with Iterational and Instructional Retiming," Accepted for publication in Journal of Embedded Computing (JEC), 2006.


  12. Z. Shao, M. Wang, Y. Chen, C. Xue, M. Qiu, L. T. Yang, E. H.-M. Sha, "Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems," Accepted for publication in IEEE Transactions on Circuits and Systems II (TCAS-II), 2006.


  13. M. Qiu, Z. Jia, C. Xue, Z. Shao and E. H.-M. Sha " Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-timeMultiproceesor DSP ," Accepted for publication in The Journal of VLSI Signal Processing Systems for Signal, Image, andVideo Technology (JVLSI), 2006.


  14. M. Qiu, C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, " Energy Minimization for Heterogeneous Wireless Sensor Networks," Accepted for publication in Journal of Embedded Computing (JEC), 2006.


  15. Q. Zhuge, C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, "Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding," in Journal of Microprocessors and Microsystems, Vol. 30, Issue 4, June 2006, pp. 173-183.


  16. Z. Shao, Q. Zhuge, M. Liu, C. Xue, E. H.-M. Sha and B. Xiao, ``Algorithms and Analysis of Scheduling for Loops with Minimum Switching", Accepted for Publication in International Journal of Computational Science and Engineering, Vol. 2, 2006.


  17. Z. Shao , J. Cao, K. C. C. Chan, C. Xue , and Edwin H.-M. Sha, "Hardware/software Optimization for Array & pointer Bound Checking Against Buffer Overflow Attacks Accepted for publication in Journal of Parallel and Distributed Computing (JPDC) Special issue on Security in Grid and Distributed Systems, Volume 66, Issue 9, Pages 1129-1136, September 2006.


  18. Z. Shao, Q. Zhuge, C. Xue and E. H.-M. Sha, ``Efficient Assignment and Scheduling for Heterogeneous DSP Systems", in IEEE Transaction on Parallel and Distributed Systems (TPDS), pp. 516-525, Vol. 16, No. 6, June, 2005.


Conference Papers

  1. T. Liu, C. Xue, Y. Zhao and M. Li, "Power-ware Variable Partitioning for DSPs with Hybrid PRAM and DRAM Main Memory,"  in Proc. 48th IEEE/ACM Design Automation Conference (DAC 2011), San Diego, CA, USA, June 5-10, 2011.


  2. L. Shi, C. Xue and X. Zhou, " Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems,"  in Proc. 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2011) in conjunction with Cyber-Physical Systems Week (CPSWEEK 2011), Chicago, IL, USA, April 11 - 14, 2011.


  3. T. Liu, C. Xue, M. Li and A. Orailoglu, "Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers,"  in Proc. ACM/IEEE Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 2011.


  4. J. Hu, C. Xue, Q. Zhuge, W. Tseng and E. H.-M. Sha, "Towards Energy Efficient Hybrid On-chip Scratch Pad Memory with Non-Volatile Memory,"  in Proc. ACM/IEEE Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 2011.


  5. Y. Huang, T. Liu and C. Xue, "Register Allocation for Write Activity Minimization on Non-volatile Main Memory,"  in Proc. The 16th Asia and South Pacific Design Automation Conference (ASPDAC 2011) , Yokohoma, Japan, 2011.


  6. W. Tseng, C. Xue, J. Hu and E. H.-M. Sha, "Optimal Scheduling to Minimize Non-Volatile Memory Access Time with Hardware Cache,"  in Proc. 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010), Madrid, Spain, Sept. 2010.


  7. J. Hu, C. Xue, W. Tseng, Y. He, M. Qiu and E. H.-M. Sha, "Reducing Write Activities on Non-volatile Memories in Embedded CMPs via Data Migration and Recomputation,"  in Proc. 2010 47th IEEE/ACM Design Automation Conference (DAC 2010), Anaheim, California, USA, June 2010.


  8. S. Liang, C. Xue, J. Hu, W. Tseng and E. H.-M. Sha, "Write Activity Reduction on Flash Main Memory via Smart Victim Cache,"   in Proc. ACM/IEEE GLSVLSI 2010, Brown University, Providence, Rhode Island, USA, May 2010.


  9. M. Li, T. Liu, Y. Zhao and C. Xue, "Analysis and Approximation for Bank Selection Instruction Minimization on Partitioned Memory Architecture"   Accepted for publication in ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2010, (LCTES 2010), Stockholm, Sweden, Apr. 2010.


  10. HE Y, C. Xue,, XU C Q, E Sha, "Co-Optimization of Memory Access and Task Scheduling on MPSoC Architectures with Multi-Level Memory",   in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp. 95-100, Taiwan, Jan 2010.


  11. T. Liu, M. Li and C. Xue, "Joint Variable Partitioning and Bank Selection Instruction Optimization on Embedded Systems with Multiple Memory Banks",   in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp. 113-118, Taiwan, Jan 2010.


  12. XU C Q, C. Xue, HE Y, E Sha, "Energy Efficient Joint Scheduling and Multi-core Interconnect Design ",   in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp. 879 ﾨC 884, Taiwan, Jan 2010.


  13. T. Liu, M. Li and C. Xue, "Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking"   Accepted for publication in 15th IEEE Real-Time and Embedded Technology and Applications Symposium, (RTAS 2009), pp 35-44, San Francisco, USA, Apr. 2009.


  14. Y. Zhao, C. Xue, M. Li and B. Hu, "Energy-aware Register File Re-Partitioning for Clustered VLIW Architectures"   Accepted for publication in 14th Asia and South Pacific Design Automation Conference, (ASPDAC 2009), Yokohama, Japan, Jan 2009.


  15. C. Xu, C. Xue, B. Hu and E. H.-M. Sha, "Computation and Data Transfer Co-Scheduling for Interconnection Bus Minimization"   Accepted for publication in 14th Asia and South Pacific Design Automation Conference, (ASPDAC 2009), Yokohama, Japan, Jan 2009.


  16. J. Hu, C. Xue, M. Qiu, W. Tseng, C. Xu, L. Zhang, and E. H.-M. Sha, "Minimizing Transferred Data for Code Update on Wireless Sensor Network"   Accepted for publication in Third International Conference on Wireless Algorithms, Systems, and Applications, (WASA 2008), pp 349-360. Oct 2008.


  17. C. Xue, Z. Yuan, G. Xing, Z. Shao, and E. H.-M. Sha, "Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems"   Accepted for publication in The 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp 237-246. Aug 2008.


  18. M Qiu, J. Wu, C. Xue, J. Hu, W. Tseng, and E. H.-M. Sha, "Loop Scheduling and Assignment to Minimize Energy while Hiding Latency for Heterogeneous Multi-Bank Memory"   Accepted for publication in The 18th IEEE International Conference on Field Programmable Logic and Applications (FPL), Heidelburg, German, Sep, 2008.


  19. C. Xue, E. H.-M. Sha, Z. Shao and M. Qiu ``Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints '' Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) , Munich, Germany, Marchl 10-14, 2008, pp 1202-1207.

  20. C. Xue, T. Liu, Z. Shao, J. Hu, Z. Jia, W. Jia and E. H.-M. Sha ``Address Assignment Sensitive Variable Partitioning and Scheduling for DSPs with Multiple Memory Banks '' Accepted in Proc. 2008 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Las Vegas, Nevada, USA, pp 1453-1456, March 30 - April 4, 2008.

  21. M. Wang, Z. Shao, H. Liu, C. Xue, ``Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP processors'' Accepted in Proc. IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), Milano, Italy, Sept. 2008.

  22. Y. Cao, Z. Shao, M. Wang, C. Xue, Y. Chen, H. Wei, T. Wang ``A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems Accepted in Proc. The 28th International Conference on Distributed Computing Systems (ICDCS 2008), Beijing, China, June 17-20, 2008.

  23. C. Xue, Z. Shao, M. Liu, Q. Zhuge and E. H.-M. Sha `` Parallel Network Intrusion Detection on Reconfigurable Platform," Accepted in Proc. 2007 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2007), Lecture Note in Computer Science (LNCS), Springer.Taiwan, Dec 2007

  24. M. Wang, Z. Shao, C. Xue, E. Sha `` Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors," Accepted in Proc. The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Aug 21-24, 2007 Korea.

  25. G. Hua, M. Wang, Z. Shao, H. Liu, C. Xue `` Real-Time Loop Scheduling with Energy Optimization via DVS and ABB for Multi-Core Embedded Systems," Accepted in Proc. 2007 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2007), Lecture Note in Computer Science (LNCS), Springer.Taiwan, Dec 2007

  26. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Scheduling with Complete Memory Latency Hiding on Multi-core architecture," Accepted in Proc. the 12th IEEE International Conference onParallel and Distributed Systems (ICPADS), Vol 1, pp. 375-382, July 2006.

  27. M. Qiu, C. Xue, Z. Shao, and E. H.-M. Sha `` Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems," Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) , Acropolis, Nice, France, April 16-20, 2007

  28. M. Liu, C. Xue, M. Qiu, and E. H.-M. Sha `` Optimizing Timing and Code Size Using Maximum Direct Loop Fusion," Accepted in Proc. The 19th International Conference onParallel and Distributed Computing Systems (ISCA PDCS 2006),San Francisco, CA, Sept. 2006.

  29. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Striping: Maximize Parallelism for Nested Loops," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer.Korea, Aug 2006

  30. M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu, and E. H.-M. Sha `` Voltage Assignment and Loop Scheduling for Energy Minimizationwhile Satisfying Timing Constraint with Guaranteed Probability," Accepted in Proc. IEEE 17th international conference on Application-specific Systems, Architectures and Processors (ASAP), Sep 2006.

  31. M. Qiu, Z. Jia, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Scheduling to Minimize Cost with Data Mining and Prefetchingfor Heterogeneous DSP," Accepted in Proc. The 18th IASTED International Conference on Parallel andDistributed Computing and Systems (IASTED PDCS),Dallas, Texas, Nov. 2006.

  32. M. Qiu, C. Xue Z. Shao, M. Liu, and E. H.-M. Sha `` Efficent Algorithm of Energy Minimization for Heterogeneour Wireless Sensor Network," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer.Korea, Aug 2006

  33. M. Qiu, Z. Shao, Qingfeng Zhuge, C. Xue, M. Liu, and E. H.-M. Sha `` Efficient Assignment with Guraranteed Probability for Heterogeneous Parallel DSP," Accepted in Proc. the 12th IEEE International Conference onParallel and Distributed Systems (ICPADS), July. 2006.

  34. M. Liu, Q. Zhuge, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Distribution and Fusion for Embedded DSP Applications Considering Code Size," Accepted in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005.

  35. M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha `` Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems," Accepted in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005.

  36. C. Xue, Z. Shao, M. Liu, M.K. Qiu and E. H.-M. Sha, `` Optimizing Nested Loops with Iterational and Instructional Retiming," Accepted in Proc. 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2005), Lecture Note in Computer Science (LNCS), Springer.Nagasaki, Japan, 6-9 December 2005

  37. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, `` Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP," Accepted in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05),Lecture Note in Computer Science (LNCS), Springer. Nagasaki, Japan, Dec. 2005.

  38. C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops," Accepted in Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), New York, New York, Sept. 2005.

  39. M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, ``Multi-level Loop Fusion with Minimal Code Size," Accepted in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, Sept. 2005.

  40. Y. Chen, Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems," Accepted in Proc. The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005(Best workshop paper).

  41. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, `` Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software", in Proc. IEEE International Conference on Information Technology (ITCC 05), Information Assurance and Security Track , Las Vegas, NV, April 2005.

  42. C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, ``Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation", in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005), Philadelphia, PA, March 2005(Winner of the Best Student paper ).

  43. Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``High-level Synthesis for DSP Applications using Heterogeneous Functional Units", in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 2005), Shanghai, China, Jan. 2005.

  44. C. Xue, Z. Shao, E. H.-M. Sha and B. Xiao, ``Optimizing Address Assignment for Scheduling Embedded DSPs," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC 2004),, pp. 64-73, Lecture Note in Computer Science (LNCS), Springer, Aizu-Wakamatsu City, Japan, August, 2004.

  45. Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu and E. H.-M. Sha, ``Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units," in 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM Proceeding, Santa Fe, Apr. 2004.

  46. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao,`` Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks," In Proc. Information Assurance and Security special track in conjunction with International Conference on Information Technology: Coding and Computing (ITCC 2004), Volume I, pp. 409-413, Las Vegas, Apr. 2004.

Awards

  1. Best Dissertation award (Title: Memory and Parallelism Optimization for Embedded Systems) of Erik Johnson School of Engineering and Computer Science, the University of Texas at Dallas, Jan 2008.

  2. Best paper award (Title: Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation) in the 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing. A total of 30 Awards are selected from a field of 1400 proceedings, and the only award in the design and implementation of Signal Processing Systems track.

  3. Best paper award (Title: Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems) in the IEEE/IFIP International Workshop on Parallel and Distributed Embedded Systems in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005.

Professional Activity

  1. Conferences

    2013
    Co-Organizer: Memory Architecture and Organization Workshop (MeAOW 2013)
    Track-chai: 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2013)
    TPC Member: The Asia and South Pacific Design Automation Conference (ASP-DAC 2013)
    TPC Member: The Design, Automation, and Test in Europe (DATE 2013)
    TPC Member: The Design Automation Conference (DAC 2013)
    TPC Member: The International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS 2013)
    TPC Member: The International Symposium on Low Power Electronics and Design (ISLPED 2013)
    TPC Member: The IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2013)

    2012
    Co-Organizer: Memory Architecture and Organization Workshop (MeAOW 2012)
    TPC Member: The International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS 2012)
    TPC Member: The International Symposium on Low Power Electronics and Design (ISLPED 2012)
    TPC Member: The Design, Automation, and Test in Europe (DATE 2012)
    TPC Member: The IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012)
    TPC Member: Languages, Compilers, Tools and Theory for Embedded Systems (LCTES 2012)

    2011
    Co-Organizer: Memory Architecture and Organization Workshop (MeAOW 2011)
    TPC Member: The Design, Automation, and Test in Europe (DATE 2011)
    TPC Member: The International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS 2011)
    TPC Member: The IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2011)

    2010
    TPC Member: The 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010)
    TPC Member: The 16th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS2010) WiP Track
    TPC Member: The 2nd Workshop on Design for Reliability 2010 (DFR'10)
    TPC Member: 2010 International Conference on Communications and Mobile Computing (CMC 2010).
    TPC Member: The 7th IEEE International Conference on Embedded Software and Systems (ICESS-2010)
    TPC Member: The 8th IEEE Symposium on Application Specific Processors (SASP 2010)
    TPC Member: The 23rd Symposium on Integrated Circuits and System Design (SCBBI 2010)
    TPC Member: The 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)
    PC Co-Chair: The 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2010)

    2009
    TPC Member: IEEE Symposium on Application Specific Processors, (SASP 2009)
    TPC Member: The 7th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC-09)
    TPC Member: The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09)
    TPC Member: The 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2009)
    General Co-Chair: The Fourth International Conferene on Embedded and Multimedia Computing (EM-Com 09 )

    2008
    Program Co-Chair: The Fifth IEEE International Symposium on Embedded Computing (SEC), 2008.
    Program Co-Chair: The Third International Workshop on Embedded Software Optimization (ESO), 2008.

Education

Ph.D. (2007) Computer Science University of Texas at Dallas
M.S. (2003) Computer Science University of Texas at Dallas
B.S. (1997) Cum Laude Computer Science & Engineering University of Texas at Arlington
B.S. (1997) Magna Cum Laude Architecture University of Texas at Arlington